Failure mode detection method and error correction method for solid state storage device
US10658065B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Aug 15, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/42
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A failure mode detection method is provided. A first default read voltage is changed to a first read retry voltage by a first increment, and a second default read voltage is changed to a second read retry voltage by a second increment. A memory cell array of a solid state storage device is successfully read according to the first and second read retry voltages. If an absolute value of the first increment minus an absolute value of the second increment is larger than a predetermined voltage value, the memory cell array is in a data retention failure mode. If the absolute value of the first increment minus the absolute value of the second increment is smaller than the predetermined voltage value, the memory cell array is in a low temperature write high temperature read failure mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.