Semiconductor die singulation
US10658240B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2019 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Mar 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a described example, a method includes: forming stress induced dislocations along scribe lanes between semiconductor dies on a semiconductor wafer using a laser; mounting a first side of the semiconductor wafer on the first side of a first dicing tape; removing a backgrinding tape from the semiconductor wafer; attaching a second dicing tape to a second side of the semiconductor wafer opposite the first side, the second dicing tape adhering to portions of the first dicing tape that are spaced from the semiconductor wafer, forming a dual taped wafer dicing assembly; separating the semiconductor dies by stretching the first dicing tape and stretching the second dicing tape; removing the second dicing tape from the semiconductor dies; and removing the semiconductor dies from the first dicing tape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.