Heterogenous 3D chip stack for a mobile processor
US10658335B2 · kind B2 · utility
3Cited by
2References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Jan 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided. The integrated circuit package includes a first die manufactured on a first wafer utilizing a first node size, a second die manufactured on a second wafer utilizing a second node size, and a substrate coupled to the second die at a plurality of bump sites on a bottom surface of the second die. The first die may be mounted on a top surface of the second die utilizing a hybrid wafer bonding technique, micro bumps, or electrode-less plating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.