Ferro-electric complementary FET
US10658384B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2019 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Sep 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A field-effect transistor includes a semiconductor substrate having first, second, third, and fourth sides, and a ferroelectric gate stack on an upper surface of the substrate. The ferroelectric gate stack includes a gate insulating layer; and a ferroelectric material layer on the gate insulating layer. Portions of the upper surface of the substrate between the first side and the ferroelectric gate stack and between the second side and the ferroelectric gate stack are doped with n-type impurities, and portions of the upper surface of the substrate between the third side and the ferroelectric gate stack and between the fourth side and the ferroelectric gate stack are doped with p-type impurities. A presence of both n and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.