Low-power scan flip-flop

US10659017B1 · kind B1 · utility

Assignee

• Marvell International Ltd. · BM

Inventors

• Krishnan S. Rengarajan · Bengaluru, IN
• Alok Chandra · Bengaluru, IN
• Chethan Ramanna · Bengaluru, IN

Key dates

• Filing date: Dec 11, 2018
• Grant date: May 19, 2020
• Expiry date: Dec 11, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K3/0372
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Disclosed are scan flip-flops (SFFs) that reduce the dynamic power consumption of a system-on-chip (SOC) that incorporates them. Each SFF includes a master latch and a slave latch, each having a driver, a feed-forward path and a feedback path. Each SFF further includes at least one shared clock-gated power supply transistor, which is controlled by either a clock signal or an inverted clock signal to selectively and simultaneously connect a voltage rail to both the driver from one latch and the feedback path of the other latch. The different SFF embodiments have different numbers of shared clock-gated power supply transistors and various other different features designed for optimal power and/or performance. For example, the different SFF embodiments have different types of slave latch drivers; different types of transistors; and/or different types of master latch drivers (e.g., a single-stage, multiple clock phase-dependent driver or a multi-stage, single clock phase-dependent driver).