Apparatus with electronic circuitry having reduced leakage current and associated methods
US10659045B2 · kind B2 · utility
0Cited by
18References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2017 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Jun 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.