Phase lock loop circuits and methods including multiplexed selection of feedback loop outputs of multiple phase interpolators
US10659064B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Feb 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase lock loop circuit includes a phase frequency detector, a voltage controlled oscillator, a phase interpolator, a clock signal selector, a selection module, a multiplexer, and a divider. The phase frequency detector compares phases of a reference clock and frequency divided output signals and generates an error signal. The voltage controlled oscillator, based on the error signal, generates a phase lock loop output signal and output clock signals. The phase interpolator phase interpolates the output clock signals to generate an interpolator output signal. The clock signal selector selects one of the output clock signals. The selection module generates a selection signal based on states of the interpolator output and selected output clock signals. The multiplexer, based on the selection signal, selects the interpolator output signal or the selected output clock signal. The divider frequency divides an output of the multiplexer to provide the frequency divided output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.