Apparatus and methods for phase synchronization of phase-locked loops
US10659065B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Apr 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.