System and method for verifying integrity of an electronic device
US10659237B2 · kind B2 · utility
2Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2017 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Feb 24, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/83
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This document discloses a system and method for verifying system integrity of an electronic device. The electronic device includes a verifier device provided within a secure environment of the electronic device and a scanner device provided within a normal environment of the electronic device whereby the secure environment comprises hardware that is isolated from the hardware in the normal environment, i.e. these two environments are hardware isolated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.