Memory access optimisation using per-layer computational mapping and memory allocation for CNN application
US10664310B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2018 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Dec 14, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of configuring a System on Chip to execute a CNN process comprising CNN layers, the method comprising, for each schedule: determining memory access amount information describing how many memory accesses are required; expressing the memory access amount information as relationships describing reusability of data; combining the relationships with a cost of writing and reading from external memory, to form memory access information; determining a memory allocation for on-chip memory of the SoC for the input FMs and the output FMs; and determining, dependent upon the memory access information and the memory allocation for each schedule; a schedule which minimises the memory access information of external memory access for the CNN layer of the CNN process; and a memory allocation associated with the determined schedule.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.