Memory controlling device and memory system including the same
US10664394B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 17, 2019 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Jan 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controlling device configured to connect to a first memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions and a second memory module used for a cache is provided. A cache controller splits an address of a read request into at least a first cache index and a first tag, and determines whether the read request is a cache hit or a cache miss by referring to a lookup logic based on the first cache index and the first tag. The cache controller instructs the memory controller to read target data of the read request from the first memory module when the read request targets to the second partition in a case where the read request is the cache miss and a write to the first partition is in progress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.