Innovative high speed serial controller testing
US10664433B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2016 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Sep 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2212/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers. According to one embodiment there is a functional semiconductor device, having therein a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; virtualized device logic embedded within the serial IO interface; a transaction originator to originate a shuttle transaction and to issue the shuttle transaction onto the device fabric directed toward the serial IO interface; in which the shuttle transaction includes a shuttle header and a shuttle payload having embedded therein one or more passenger transactions for issuance onto the device fabric; in which the virtualized device logic is to receive the shuttle transaction at the serial IO interface via the device fabric; in which the virtualized device logic is to strip the shuttle header from the shuttle transaction to expose the one or more passenger transactions; and in which the virtualized device logic is to issue the one or more passenger transactio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.