Bandwidth test in networking System-on-Chip verification
US10664566B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2017 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Jan 2, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosed technology relate to techniques of bandwidth test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates dispatch time information with messages when the messages are dispatched by a hardware model of a circuit design implemented in the reconfigurable hardware modeling device. The dispatch time information of a particular message includes information about when, based on a model time reference provided in the reconfigurable hardware modeling device, the particular message is dispatched by the hardware model of the circuit design. The messages and the dispatch time information are sent to a traffic analysis device, which determines bandwidth information of ports of the circuit design based on the dispatch time information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.