End-to-end memory networks
US10664744B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2017 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Feb 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/09
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments are disclosed for predicting a response (e.g., an answer responding to a question) using an end-to-end memory network model. A computing device according to some embodiments includes embedding matrices to convert knowledge entries and an inquiry into feature vectors including the input vector and memory vectors. The device further execute a hop operation to generate a probability vector based on an input vector and a first set of memory vectors using a continuous weighting function (e.g., softmax), and to generate an output vector as weighted combination of a second set of memory vectors using the elements of the probability vector as weights. The device can repeat the hop operation for multiple times, where the input vector for a hop operation depends on input and output vectors of previous hop operation(s). The device generates a predicted response based on at least the output of the last hop operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.