Pixel compensating circuit and pixel compensating method
US10665159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2018 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Dec 27, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0626
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In the compensating circuit, a second thin film transistor (TFT) are connected to a gate and drain of a first TFT, and a source of the first TFT receives a constant DC voltage signal, and the second TFT receives a scan signal of nth stage; a third TFT is connected to the drain of the first TFT, is connected to a common ground through a light emitting device, and receives an enable signal; a fourth TFT receives a scan signal of n−1th stage, and is connected to a first end of a storage capacitor and the gate of the TFT, and a second end of the storage capacitor is connected to a fifth TFT and a sixth TFT; the fifth TFT receives a data signal and the scan signal of nth stage, respectively; the sixth TFT is connected to the common ground and receives the enable signal, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.