Memory device testing
US10665319B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2018 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Nov 29, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches for testing memory devices, such as DRAMs, are described that can quickly identify various potential storage issues. The memory space for a device can be divided into subspaces that can be tested concurrently. A starting address is determined for each memory sub-space, and addresses are identified that are within a Hamming distance of the starting address, where a single Hamming distance or multiple Hamming distances can be used. Once a list of addresses is generated, a test pattern can be written to, and read from, the corresponding addresses. Differences from the expected pattern can be indicative of problems with the memory device, whether before user deployment or while storing live data. If there are specific problems suspected, targeted testing can be utilized that does not test the entirety of the memory space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.