Method (and related apparatus) that reduces cycle time for forming large field integrated circuits
US10665455B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2018 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Nov 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.