Semiconductor memory including pads arranged in parallel
US10665558B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2018 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Jul 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1434
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory includes a plurality of first pads arranged in a first direction, a plurality of second pads arranged parallel to the plurality of first pads and in the first direction, a plurality of third pads arranged in a second direction perpendicular to the first direction, and a plurality of fourth pads arranged in the second direction. The semiconductor memory further includes first interconnection wires extending from the plurality of first pads in the second direction, the first interconnection wires being connected to the plurality of third pads, and second interconnection wires extending from the plurality of second pads in an opposite direction to the second direction, the second interconnection wires being connected to the plurality of fourth pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.