Semiconductor memory device and method of fabricating the same
US10665592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2018 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Aug 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.