Air void structures for semiconductor fabrication
US10665752B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2017 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Dec 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/01335
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide for mechanisms for forming air voids for semiconductor fabrication. In accordance with some embodiments, a method for forming air voids may include forming a first semiconductor layer including a first group III material and a second group III material on a substrate; forming a plurality of air voids in the first semiconductor layer by removing at least a portion of the second group III material from the first semiconductor layer; and forming a second semiconductor layer on the first semiconductor layer. The second semiconductor layer may include an epitaxial layer of a group III-V material. In some embodiments, the first group III material and the second group III material may be gallium and indium, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.