Elimination of secondary fuses in high power solid state power controllers
US10666042B2 · kind B2 · utility
1Cited by
3References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 14, 2017 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Mar 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H3/066
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Embodiments include a technique for eliminating secondary fuses in high power solid state power controllers, the technique includes controlling gate power provided to a field effect transistor array, and detecting a failure mode. The technique also includes disabling the gate power based at least in part on detecting the failure mode, and restoring the gate power responsive to resolving the failure mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.