High-speed low-power-consumption dynamic comparator
US10666243B2 · kind B2 · utility
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Key dates
| Filing date | Jul 7, 2016 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Aug 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/003
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed low-power-consumption dynamic comparator includes a latch, an AND gate, a delay unit, and an XNOR gate. According to the high-speed low-power-consumption dynamic comparator, the output signal is generated through the XNOR gate from the comparator output signals Dp and Dn. The output signal and the control signal clk1 generate the control signal of the NMOS transistor P10 through the AND gate, so that the problem of static power consumption in a conventional comparator is solved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.