Partitioned delta-sigma modulator for high-speed applications
US10666286B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2019 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Jan 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A partitioned delta-sigma modulator for high-speed applications includes a plurality of modulation stages arranged in parallel to input and output terminals of the modulator and interconnected to one another in series. In some aspects, each of the plurality of modulation stages is configured to combine a first error signal from a prior modulation stage of the plurality of modulation stages with a first digital signal to produce an adder signal. In some aspects, the first error signal includes a delay from the prior modulation stage. Each of the plurality of modulation stages is also configured to convert the adder signal having a first bit width into a quantized signal having a second bit width smaller than the first bit width. Each of the modulation stages is also configured to provide a second error signal based on the quantized signal to a subsequent modulation stage of the plurality of modulation stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.