Maximum likelihood sequence estimation circuit, receiving device, and maximum likelihood sequence estimation method
US10666299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2016 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Dec 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03585
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A maximum likelihood sequence estimation circuit includes: a signal extraction unit that estimates a reception sample signal including a preceding wave component and a reception sample signal including a delayed wave component from a plurality of reception sample signals sampled from a reception signal at sample intervals shorter than symbol intervals, and extracts, based on an estimation result, both first reception sample signals and second reception sample signals from the plurality of reception sample signals at the symbol intervals; and a maximum likelihood sequence estimation unit that estimates a maximum likelihood sequence using the first reception sample signals extracted and the second reception sample signals extracted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.