Method and apparatus to minimise the onset and recovery time of a silicon photomultiplier
US10670742B2 · kind B2 · utility
1Cited by
4References
26Claims
0Family size
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Key dates
| Filing date | Oct 5, 2017 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Jul 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F77/959
- WIPO fieldEnvironmental technology
- WIPO sectorChemistry
Abstract
Silicon photomultiplier circuitry is provided that comprises at least one silicon photomultiplier pixel, each pixel comprising a plurality of silicon photomultiplier microcells. The silicon photomultiplier circuitry comprises control circuitry adapted to maintain a substantially constant voltage on a connection node between microcells of the pixel. The control circuitry is adapted to minimise the onset and recovery time of an output signal by maintaining a substantially constant voltage on the connection node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.