Patent · US Active

Hierarchical sparse tensor compression method in artificial intelligent devices

US10671288B2 · kind B2 · utility

1Cited by

0References

5Claims

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Assignee

Nanjing Iluvatar CoreX Technology Co., Ltd. · CN

Inventors

Pingping Shao · San Jose, US
Jiejun Chen · Shanghai, CN
Yongliu Wang · Shanghai, CN

Key dates

Filing date	Dec 31, 2018
Grant date	Jun 2, 2020
Priority date	—
Expiry date	Jan 12, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06N5/022
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A hierarchical sparse tensor compression method based on artificial intelligence devices, in DRAM, not only saves the storage space of the neuron surface, but also adds a meta-surface to the mask block. When reading data, the mask is first read, then the size of the non-zero data is calculated, and only these non-zero data are read to save DRAM bandwidth. In the cache, only non-zero data is stored, so the required storage space is reduced. When processing data, only non-zero data is used. The method uses a bit mask to determine if the data is zero. There are three levels in the hierarchical compression scheme: tiles, lines, and points, reading bitmasks and non-zero data from DRAM, and saving bandwidth by not reading zero data. When processing data, if their bit mask is zero, the tile data may be easily removed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.