Lazy data loading for improving memory cache hit ratio in DAG-based computational system
US10671436B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2018 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Nov 27, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/608
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for improving a hit ratio of a buffer cache in a system in which vertices of a DAG have tasks that generate intermediate data stored in the buffer cache. The method tracks (i) a buffer cache usage by vertices that have finished running and (ii) a current available buffer cache space. Responsive to a new task being runnable and having dependent parent vertices, the method estimates a total buffer cache usage of current running vertices based on a partial result of the current running vertices. Responsive to the estimate exceeding current available buffer cache space, the method (i) selects a vertex having a most amount of intermediate data stored in the buffer cache for its dependent parent vertices, and (ii) increases a priority of the tasks in the selected vertex to obtain prioritized tasks. The method executes the prioritized tasks earlier than other remaining runnable tasks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.