Systems and methods for obfuscating a circuit design
US10671700B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2019 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Sep 9, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.