DRAM with simultaneous read and write for multiwafer image sensors
US10672101B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2019 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Mar 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/79
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A bond-per-pixel-block image sensor has a pixel array including multiple pixel blocks with selection circuitry to couple signals to an ADC. The image sensor has an image RAM of DRAM superblocks, each superblock with multiple DRAM blocks each having tristate output driving an image RAM output bus, and data input from several of the ADCs. Each DRAM block has an address multiplexor coupled to read and write addresses. DRAM blocks of each superblock are written simultaneously with data wider than a width of the image RAM output bus. A method of capturing and processing images includes reading a first image frame from pixels of a pixel block through ADCs; writing digital pixel data for the first image frame in a first DRAM superblock; and reading pixel data into an alignment buffer. The method includes overlapping reading the first image frame with writing a second image frame into a second superblock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.