Method of self-testing and reusing of reference cells in a memory architecture
US10672455B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2019 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | May 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.