Integrated circuit formed from a stack of two series-connected chips
US10672746B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2017 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Nov 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a first chip including a high-voltage depletion-mode transistor and a second chip including an enhancement-mode device. The chips have first and second gate contact pads, first and second source contact pads and first and second drain contact pads, respectively, on their front sides. Chips are joined together via their front sides, and the area of the first chip is larger than that of the second chip. The first chip includes an additional contact pad on its front side that is electrically insulated from the high-voltage depletion-mode transistor and that contacts the second gate contact pad. The first gate contact pad contacts the second source contact pad and/or the first source contact pad contacts the second drain contact pad. The first gate contact pad and the additional contact pad extend at least partially into a peripheral portion of the first chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.