Methods of manufacturing transistors including forming a depression in a surface of a covering of resist material
US10672765B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2016 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Aug 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a transistor comprising providing a substrate, a region of semiconductive material on the substrate, and a region of electrically conductive material on the region of semiconductive material; forming a covering of resist material over said regions; forming a depression in a surface of the covering of resist material that extends over a first portion of said region of conductive material, said first portion separating second and third portions of the conductive region; removing resist material located under said depression to form a window through said covering, exposing said first portion; removing said first portion to expose a connecting portion of the region of semiconductive material that connects the second and third portions; forming a layer of dielectric material over the exposed connecting portion; and forming a layer of electrically conductive material over said layer of dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.