Active CMOS recovery units for wireless power transmission
US10673351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2018 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Jun 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/23
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A rectifying circuit includes, in part, first and second NMOS transistors, an impedance matching network, and an RF block circuit. The source and gate terminals of the first NMOS transistor respectively receive the ground potential and a biasing voltage. The second NMOS transistor has a gate terminal coupled to the drain terminal of the first NMOS transistor, a drain terminal coupled to the gate terminal of the first NMOS transistor, and a source terminal receiving the ground potential. The impedance matching network is disposed between the antenna and the drain terminals of the first and second NMOS transistors. The RF block circuit is coupled between the drain terminals of the first and second NMOS transistors and the output terminal of the rectifying circuit. The RF block circuit is adapted to prevent the RF signal from flowing into the output terminal of the rectifying circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.