Optimized multi gain LNA enabling low current and high linearity including highly linear active bypass
US10673401B2 · kind B2 · utility
5Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2018 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Jul 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G2201/504
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.