Delay-based residue stage
US10673453B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2019 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Jul 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter has a logic gate for generating an output signal having a delay corresponding to a delay between input signals. The logic gate includes inputs for receiving the input signals, and an output for outputting the output signal. A delay comparator generates a digital signal representative of the order of the input signals, and generates a delay signal having a delay corresponding to the delay between the input signals. The delay comparator has inputs for receiving the input signals, a digital output for outputting the digital signal, and a delay output for outputting the delay signal. A delay-based analog-to-digital converter, with a front stage and successive residual stages, is also disclosed. A delay comparator having merged comparator, sign-out, and delay-out circuits, and which may be operated within one of successive stages, without a clock, is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.