System and method for protecting a cryptographic device against fault attacks while performing cryptographic non-linear operations using linear error correcting codes
US10673610B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | May 27, 2016 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Dec 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/34
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system, method and computer-readable storage medium with instructions for protecting an electronic device against fault attack. Given a data represented as an input codeword of a systematic linear error correcting code, the technology provides the secure computation of the output codeword corresponding to the result of the non-linear function applied to this data. Other systems and methods are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.