Continuous time linear equalizer
US10673660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2019 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Jul 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03541
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.