Aggregating non-imaging SPAD architecture for full digital monolithic, frame averaging receivers
US10677899B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2017 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Nov 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/107
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present disclosure relates to systems and methods that include a monolithic, single-chip receiver. An example system includes a plurality of macropixels, each made up of an array of single photon avalanche diodes (SPADs). The system also includes a plurality of pipelined adders communicatively coupled to a respective portion of the plurality of macropixels. The system additionally includes a controller configured to carry out operations. The operations include during a listening period, receiving, at each pipelined adder of the plurality of pipelined adders, respective photosignals from the respective portion of the plurality of macropixels. The operations also include causing each pipelined adder of the plurality of pipelined adders to provide an output that includes a series of frames that provide an average number of SPADs of the respective portion of the plurality of macropixels that were triggered during a given listening period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.