Systems and methods for reduced boot power consumption using early BIOS controlled CPU P-states to enhance power budgeting and allocation
US10678321B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2018 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Dec 6, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for reduced boot power consumption using early BIOS controlled CPU power states to enhance power budgeting and allocation. An information handling system may include a server. The server may include a central processing unit (CPU), a memory, a non-volatile random-access memory (NVRAM) device, a performance state (P-state) limiting indicator stored in the NVRAM device, a P-state value stored in the NVRAM, and a basic input/output system (BIOS) stored in the memory. The BIOS may read a power state limiting indicator stored in the NVRAM device and when the power state limiting indicator indicates that power state limiting is enabled, read a power state value stored in the NVRAM, and program the power state of the CPU to the power state value to cause the CPU to limit power supplied to the CPU to the power state value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.