Patent · US Active

Peripheral based memory safety scheme for multi-core platforms

US10678474B1 · kind B1 · utility

0Cited by

4References

17Claims

0Family size

Assignee

NXP B.V. · NL

Inventors

Marcel Medwed · Graz, AT
Jan Hoogerbrugge · Eindhoven, NL
Ventzislav Nikov · Haasrode, BE

Key dates

Filing date	Nov 30, 2018
Grant date	Jun 9, 2020
Priority date	—
Expiry date	Dec 15, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/1016
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computing system using low-fat pointers, including: a memory configured to be accessed by the low-fat pointers; a processing core configured to access the memory; an interrupt controller configured to receive interrupts and to communicate interrupts to processes running on the processing core; and a memory safety peripheral configured to receive a pointer request, wherein the pointer is a low-fat pointer and to verify that the pointer request is within required memory bounds.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.