Method and system for coordinating baseline and secondary prefetchers
US10678692B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2017 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Sep 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor comprises a first prefetcher to generate prefetch requests to prefetch data into a mid-level cache; a second prefetcher to generate prefetch requests to prefetch data into the mid-level cache; and a prefetcher selector to select a prefetcher configuration for the first prefetcher and the second prefetcher based on at least one memory access metric, wherein the prefetcher configuration is to specify whether the first prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of a particular page and whether the second prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of the particular page.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.