Error reducing matrix generation
US10679718B2 · kind B2 · utility
2Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2017 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Oct 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses, systems, methods, and computer program products are disclosed for error reducing matrix generation. An apparatus includes a test circuit that performs a test on a set of memory cells. An apparatus includes a masking circuit that determines a masking array based on a test performed on a set of memory cells. An apparatus includes a decoding circuit that decodes encoded data from a set of memory cells based on a masking array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.