Mask and metal wiring of a semiconductor device formed using the same
US10679940B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2016 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Sep 14, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A mask including a mask substrate including a cell exposure region and a peripheral exposure region, the cell exposure region configured to expose a metal layer in a cell region of a semiconductor device, the peripheral exposure region configured to expose a metal layer in a peripheral region of the semiconductor device, a first mask pattern configured to expose the metal layer in the peripheral exposure region of the mask substrate to form a signal metal pattern, and a second mask pattern configured to expose the metal layer in the peripheral exposure region of the mask substrate to form a dummy metal pattern, the second mask pattern being adjacent to the first mask pattern, and the second mask pattern having a substantially same width as a width of the first mask pattern may be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.