Field-effect transistor comprising germanium and manufacturing method thereof
US10680108B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2016 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Dec 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosed technology generally relates to semiconductor devices, and more particularly to transistors comprising germanium (Ge) in the channel, and to methods of manufacturing thereof. In one aspect, a field-effect transistor (FET) comprises an active region comprising germanium (Ge) and a gate stack formed on the active region. The gate stack comprises a Si-comprising passivation layer formed on the active region, an interfacial dielectric layer comprising SiOx (x>0) formed on the passivation layer, a dielectric capping layer comprising an interface dipole-forming material formed on the interfacial dielectric layer, a high-k dielectric layer formed on the dielectric capping layer and a gate electrode layer formed on the high-k dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.