Patent · US Active

Digital phase locked loop frequency estimation

US10680619B2 · kind B2 · utility

0Cited by

1References

21Claims

0Family size

Assignee

Intel IP Corporation · US

Inventors

Elan Banin · Raanana, IL
Roy Amel · Haifa, IL
Ran Shimon · Ramat Gan, IL
Ashoke Ravi · Portland, US
Nati Dinur · Haifa, IL

Key dates

Filing date	Oct 25, 2018
Grant date	Jun 9, 2020
Priority date	—
Expiry date	Oct 25, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2027/0067
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.