Decoder circuit and decoder circuit design method
US10680641B2 · kind B2 · utility
0Cited by
7References
7Claims
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Key dates
| Filing date | Aug 13, 2019 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Aug 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The n-bit decoder circuit includes 2n base circuits each outputting, as the output signal OA, ‘0’, ‘1’ or the input signal IA depending on setting of selection signals S<1:0>; and the (n−1)-bit decoder circuit. The (n−1)-bit decoder circuit includes 2(n-1) base circuits and an (n−2)-bit decoder circuit in cases of n≥3, and includes the 1-bit decoder circuit in cases of n=2. The 1-bit decoder circuit outputs ‘00’ in cases of the binary input BIN<0>=‘0’ and outputs ‘01’ in cases of the binary input BIN<0>=‘1’ as thermometer outputs THM(1)<1:0>.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.