Methods and apparatus for managing power with an inter-processor communication link between independently operable processors
US10684670B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2019 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Apr 22, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.