Method and device for on-chip repetitive addressing
US10684946B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2016 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Dec 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method may include: partitioning data on an on-chip and/or an off-chip storage medium into different data blocks according to a pre-determined data partitioning principle, wherein data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block; and a data indexing step for successively loading different data blocks to at least one on-chip processing unit according a pre-determined ordinal relation of a replacement policy, wherein the repeated data in a loaded data block being subjected to on-chip repetitive addressing. Data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block, and the data partitioned into the same data block can be loaded on a chip once for storage, and is then used as many times as possible, so that the access is more efficient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.