Semiconductor storage device
US10685701B2 · kind B2 · utility
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4Claims
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Assignee
Inventor
Key dates
| Filing date | May 8, 2019 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | May 8, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor storage device having a dual-port SRAM cell with a smaller area and low-current consumption and securing a good static noise margin. The semiconductor storage device includes a memory cell circuit constituting the dual port SRAM cell comprised of six transistors. When driving the first or second word line, a word line driver circuit lowers a high-level voltage which is to be output to the driven word line such that the high-level voltage is lower than a high-level voltage which is to be output to both of the first and second word lines when driving both the first and second word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.