Memory device
US10685707B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2019 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Apr 9, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, each of the plurality of memory cells including a switching element and an information storage element connected to the switching element and containing a phase-change material, a decoder unit configured to determine a selected word line and a selected bit line connected to a selected memory cell to read data, among the plurality of memory cells, and a current compensation circuit configured to remove a leakage current from the selected word line, the leakage current corresponding to a sun of off-currents flowing in unselected bit lines, excluding the selected bit line, among the plurality of bit lines, from the selected word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.